The present invention relates to a circuit for performing discrete cosine transform (DCT) and, more particularly, to a DCT circuit suitable for integrated circuit implementation and readily applicable to inverse DCT (IDCT) and two-dimensional DCT as well.
DCT belongs to a family of orthogonal transform techniques and achieves highly efficient coding of moving picture signals such as a television signal. Since a DCT circuit needs a rapid convolution operation capability, it in most cases has been implemented with a digital signal processor (DSP) or similar signal processing LSI. Today, exclusive LSI's for DCT operations (DCT LSI) in the form of chips are in development with the help of advancing device fabrication technologies, extended studies on DCT high-speed operation algorithm, etc. Such a DCT LSI was reported by J. C. Carlach et al. in a paper entitled "TCAD: a 27 MHz 8.times.8 Discrete Cosine Transform Chip" at ICASSP '89 held in Glasgow, Scotland in May 23-26, 1989. The DCT LSI disclosed in this paper executes 8-point one-dimensional DCT by Duhamel Algorithm which will be described. Specifically, this DCT LSI transforms eight input data (assume data x.sub.0 to x.sub.7) into eight terms (x.sub.0 .+-.x.sub.7), (x.sub.1 .+-.x.sub.6), (x.sub.2 .+-.x.sub.5) and (x.sub.3 .+-.x.sub.4) by addition and subtraction, thereby halving the required number of times of multiplication by DCT coefficients. Further, the DCT LST converts the value of each term into an read address by a decoder to address a ROM which has stored operation results beforehand, the ROM thus serving as a multiplier. The drawback with the DCT LSI proposed by Carlach et al. is that regarding 8-point DCT, it inputs eight input data x.sub.0 to x.sub.7 at the same time and, therefore, needs complicated circuitry for generating the above-mentioned eight terms (referred to as "shuffling stage" in the paper). Moreover, the paper does not describe any specific circuitry for using DCT LSI as IDCT LSI.